1. Field of the Invention
The present invention relates to a semiconductor structure having a compensated resistance in an LDD area and to a method for producing the same, in particular to a semiconductor structure having a compensated resistance in an LDD area. The present invention relates in particular to MOS transistors (MOS=metal oxide semiconductor) wherein between a source area and a drain area a lightly doped drain area is provided which is referred to as an LDD area (LDD=lightly doped drain). In particular, the present invention relates to LDMOS transistors and the production of the same (LDMOS=lateral diffused MOS).
2. Description of the Related Art
In MOS transistors for high power applications or in LDMOS transistors for high-frequency power applications between the gate structure and the drain area the LDD area is generated, e.g. by an implantation. In LDMOS transistors before the generation of the source area on the source side of the gate the required channel implantation is introduced which is then diffused under the gate structure in a subsequent temperature step.
Preferably, in LDMOS transistors for high frequency power applications, on the side of the gate structure facing the drain area, a longer n-doped LDD area is implanted. There are continuous trials to improve the performance of such an LDMOS transistor. An improvement of the performance is for example achieved by an increase of the breakdown voltage or by an improvement of the high frequency characteristics, for example by shielding the gate structure against the drain area. In order to achieve this, the prior art proposes to implant a flat buried area having a p-doping in the n-doped LDD area. This is for example described by H. Söderbärg et al. in “Integration of a Novel High-Voltage Giga-Hertz DMOS Transistor into a Standard CMOS Process”, IEEE IEDM Washington 1995, pp. 975–978 and by E. Gebara et al. in “Output Power Characteristics of High Voltage LDMOS Transistors”, GHz 2000 Symp. 5th Symp. on Giga-Hertz-Electronics, Proc., Göteborg, p. 13, 14th Mar. 2000, pp. 78—78.
The disadvantage of the preceding methods is that by implantation of the p-region the resistance of the LDD area is increased which is compensated by a correspondingly suitable increase of the doping of the LDD area and by introducing an additional n-doping in the LDD area in the area of the p-region.
In the prior art, a deep LDD area is used which additionally reaches far below the gate structure. The deep LDD area results in the fact that the additionally introduced doping in the p-region only represents a relatively low counter doping to the n-doping of the LDD area, so that the resistance of the LDD area in the area of the p-region only slightly increases. Further, above the p-region an additional n-doping is introduced, so that the p-region is completely buried in the LDD area.
It is a disadvantage of the deep LDD area that the same reaches far below the gate structure which leads to an increase of the drain-gate-capacity which is in particular undesirable in the RF area. However, this deep LDD area which therefore reaches below the gate structure may not be omitted in order to guarantee the shielding of the gate structure with a simultaneous compensation of the resistance increase due to the p-region. Suggestions for a compensation of the resistance increase in comparatively flat LDD areas which do not reach below the gate structure and therefore comprise a low gate-drain-capacity are not known in the prior art.